This application claims benefit of priority under 35 USC xc2xa7119 to Japanese Patent Application No. 2001-107409 filed on Apr. 5, 2001, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention pertains to a technique for specifying a defect causing an electric failure by checking electric failure data obtained in a test process of a semiconductor device against defect data obtained in an inspection process.
2. Description of Related Art
As semiconductor integrated circuit technology rapidly progresses, the number of chips mounted on a single wafer is dramatically increasing and the chips are becoming more complicated. Consequently, in order to specify the cause of a defect, it is very important to specify the defect truly responsible for an electric failure by checking defect data indicative of the existence and position of foreign matter, defects, or the like on a semiconductor wafer obtained in a defect inspection process in a semiconductor device fabricating process against fail bit map (herein below, abbreviated as xe2x80x9cFBMxe2x80x9d) data indicative of the position of an electric failure in a semiconductor chip obtained in a test process.
In the defect inspection process, coordinates and the size of a defect are detected. A coordinate system of defect data as a result of detection is a rectangular physical coordinate system having one origin for one chip. In contrast, for the FBM data obtained in the test process, a coordinate system in which the position of an electric failure corresponds to a physical address is used.
Therefore, in the case of checking the defect data against the FBM data in such a manner, coordinate transformation has to be performed so that the coordinate system of the defect data and the coordinate system of the FBM data coincide with each other. Usually, a failure address (physical address) of the FBM data is subjected to coordinate transformation bit by bit so as to make the coordinate system of the FBM data coincide with the coordinate system of the defect data and, after that, the defect data and the FBM data are checked against each other.
Conventionally, such a coordinate transformation means is realized by a mathematical expression, a program, or the like generated by human means. Consequently, as the scale and complication of a memory cell increases, the coordinate transformation program itself becomes more complicated, the time required for generation becomes longer, and human error increases.
To generate such coordinate transformation means, knowledge of the configuration of a memory cell and the like of a product as an object and, further, skills of generating the necessary mathematical expression and program are necessary. Therefore, engineers satisfying the conditions are limited.
Further, the propriety of the generated coordinate transformation means is verified by sampling representative points significant for verification, transmitting data of a result of coordinate transformation by the generated coordinate transformation means to a Scanning Electron Microscope (SEM) or the like, and observing an actual wafer with the human eye to see whether a stage is moved to a target position or not. The time required for verification is consequently very long and the number of sampling points for verification is limited. Therefore, time and a cost to need for generating and verification of the transformation means increase, and difficulty of improvement of the reliability increases.
A system for transforming a coordinate assigned in a semiconductor device according to an embodiment of the invention includes: a layout display unit configured to obtain an arbitrary point in layout data of the semiconductor device displayed on a screen of a display device as a coordinate value of an FBM physical coordinate system indicative of a physical position on the semiconductor device; a pattern defining unit configured to define a relationship between an FBM physical address and the FBM physical coordinates using a pattern tree obtained by combining an array pattern, defining lining direction, interval, and the number of components to be disposed at equal intervals, with a random pattern, defining the relationship between the FBM physical address as a coordinate system of FBM data indicative of an electric failure position obtained by a test process of the semiconductor device and the FBM physical coordinates in a one-to-one corresponding manner; and a forward transformation program generating unit configured to generate a forward transformation program to transform the FBM physical address of the semiconductor device into the FBM physical coordinates from the pattern defined.
A computer implemented method for transforming a coordinate in a semiconductor device according to an embodiment of the invention includes: obtaining an arbitrary point in layout data of the semiconductor device displayed on a screen of a display device as a coordinate value of an FBM physical coordinate system indicative of a physical position on the semiconductor device; defining a relationship between an FBM physical address and the FBM physical coordinates using a pattern tree obtained by combining an array pattern, defining lining direction, interval, and the number of components to be disposed at equal intervals, with a random pattern, defining the relationship between the FBM physical address as a coordinate system of FBM data indicative of an electric failure position obtained by a test process of the semiconductor device and the FBM physical coordinates in a one-to-one corresponding manner; generating a forward transformation program to transform the FBM physical address of the semiconductor device into the FBM physical coordinates from the pattern defined; and transforming the FBM physical address of the semiconductor device into the FBM physical coordinates by executing the forward transformation program.
A program for controlling a coordinate transformation system for a semiconductor device according to an embodiment of the invention includes: obtaining a position of a component to which an address in a pattern belongs and an address in a lower pattern in a pattern tree in a case where the pattern defined is an array pattern; obtaining physical coordinates in the pattern corresponding to the address in the pattern and the address in the lower pattern in the pattern tree in a case where the pattern defined is a random pattern; executing the above process on each pattern downward from the highest pattern to the lowest pattern in the pattern tree, the pattern tree obtained by combining the array pattern, defining a lining direction, interval, and the number of components disposed at equal intervals, with the random pattern, defining a relationship between an FBM physical address as a coordinate system of FBM data indicative of an electric failure position obtained by a test process of the semiconductor device and the FBM physical coordinates indicative of a physical position on the semiconductor device in a one-to-one corresponding manner; and obtaining a coordinate value finally derived as an FBM physical coordinate value corresponding to the FBM physical address value to be transformed.